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ltm2883 1 2883f typical a pplica t ion fea t ures descrip t ion spi/digital or i 2 c module isolator with adjustable 12.5v and 5v regulated power the ltm ? 2883 is a complete galvanic digital module ? isolator. no external components are required. a single 3.3v or 5v supply powers both sides of the interface through an integrated, isolated dc/dc converter. a logic supply pin allows easy interfacing with different logic levels from 1.62v to 5.5v, independent of the main supply. available options are compliant with spi and i 2 c (master mode only) specifications. the isolated side includes 12.5v and 5v nominal power supplies, each capable of providing more than 20ma of load current. each supply may be adjusted from its nominal value using a single external resistor. coupled inductors and an isolation power transformer provide 2500v rms of isolation between the input and out- put logic interface. this device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. communication is uninterrupted for common mode transients greater than 30kv/s. l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks and easy drive, hot swap, softspan and timerblox are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. isolated 4mhz spi interface a pplica t ions n ul rated 6-channel logic isolator: 2500v rms ul recognized ? file #e151738 n isolated adjustable dc power: 3v to 5v at up to 30ma 12.5v at up to 20ma n no external components required n spi (ltm2883-s) or i 2 c (ltm2883-i) options n high common mode transient immunity: 30kv/s n high speed operation: 10mhz digital isolation 4mhz/8mhz spi isolation 400khz i 2 c isolation n 3.3v (ltm2883-3) or 5v (ltm2883-5) operation n 1.62v to 5.5v logic supply n 10kv esd hbm across the isolation barrier n common mode working v oltage: 560v peak n low current shutdown mode (<10a) n low profile (15mm 11.25mm 3.42mm) bga package n isolated spi or i 2 c interfaces n industrial systems n test and measurement equipment n breaking ground loops ltm2883 operating through 35kv/s cm transient 2883 ta01a on cs cs2 ltm2883-5s v l v cc 5v gnd gnd2 sdi sdoe sdi2 do2 sck sck2 cs sdi sck cs sdi sck av + v ? av ? av cc2 v + v cc2 sdo sdo2 sdo sdo i2 do1 i1 isolation barrier 5v at 20ma 12.5v at 20ma ?12.5v at 15ma 20ns/div 2v/div 2v/div sck sd0 sck2 = sd02 200v/div 2883 ta01b repetitive common mode transients
ltm2883 2 2883f a bsolu t e maxi m u m r a t ings v cc to gnd .................................................. C 0.3v to 6v v l to gnd .................................................... C0 .3v to 6v v cc2 , av cc2 , av + to gnd2 ........................... C 0.3v to 6v v + to gnd2 ................................................ C 0.3v to 16v v C , av C to gnd2 ......................................... 0 .3v to C16v logic inputs di1, sck, sdi, cs , scl, sda, sdoe , on to gnd .................................. C 0.3v to (v l + 0.3v) i1, i2, sda2, sdo2 to gnd2 ........................ C 0.3v to (v cc2 + 0.3v) (note 1) logic outputs do1, do2, sdo to gnd .............. C 0.3v to (v l + 0.3v) o1, sck2, sdi2, cs2 , scl2 to gnd2 ........................ C 0.3v to (v cc2 + 0.3v) operating temperature range (note 4) ltm2883c ......................................... 0 c t a 70c ltm2883i ..................................... C 40c t a 85c ltm2883h ................................... C 40c t a 105c maximum internal operating temperature ............ 1 25c storage temperature range .................. C 55c to 125c peak body reflow temperature ............................ 24 5c ltm2883-i ltm2883-s v cc gnd do1 av + av ? gnd2 i1 bga package 32-pin (15mm 11.25mm 3.42mm) top view av cc2 f g h l j k e a b c d 21 43 5 6 7 8 dncdo2 sdascl di1 gnd on v l dnci2 sda2scl2 o1 v cc2 v ? v + t jmax = 125c, ja = 30c/w, jc(bottom) = 15.7c/w, jc(top) = 25c/w, jboard = 14.5c/w values determined per jesd51-9, weight = 1.2g v cc gnd do1 av + av ? gnd2 i1 bga package 32-pin (15mm 11.25mm 3.42mm) top view av cc2 f g h l j k e a b c d 21 43 5 6 7 8 do2sdo sdisck cs sdoe on v l i2sdo2 sdi2sck2 cs2 v cc2 v ? v + t jmax = 125c, ja = 30c/w, jc(bottom) = 15.7c/w, jc(top) = 25c/w, jboard = 14.5c/w values determined per jesd51-9, weight = 1.2g p in c on f igura t ion
ltm2883 3 2883f ltm2883 c y -3 s #pbf lead free designator pbf = lead free logic option i = inter-ic (i 2 c) bus s = serial peripheral interface (spi) bus input voltage range 3 = 3v to 3.6v 5 = 4.5v to 5.5v package type y = ball grid array (bga) temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C40c to 105c) product part number o r d er i n f or m a t ion p ro d uc t s elec t ion g ui d e part number part marking * package input voltage logic option ltm2883-3i ltm2883y-3i bga 3v to 3.6v inter-ic bus (i 2 c) ltm2883-3s ltm2883y-3s bga 3v to 3.6v serial peripheral interface bus (spi) ltm2883-5i ltm2883y-5i bga 4.5v to 5.5v inter-ic bus (i 2 c) ltm2883-5s ltm2883y-5s bga 4.5v to 5.5v serial peripheral interface bus (spi) consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ this product is moisture sensitive. for more information go to: http://www.linear.com/packaging/ e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. specifications apply to all options unless otherwise noted. symbol parameter conditions min typ max units input supplies v cc input supply range ltm2883-3 ltm2883-5 l l 3 4.5 3.3 5 3.6 5.5 v v v l logic supply range ltm2883-s ltm2883-i l l 1.62 3 5 5.5 5.5 v v i cc input supply current on = 0v ltm2883-3, on = v l , no load ltm2883-5, on = v l , no load l l l 0 25 19 10 35 28 a ma ma i l logic supply current on = 0v ltm2883-s, on = v l ltm2883-i, on = v l l 0 10 10 150 a a a
ltm2883 4 2883f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. specifications apply to all options unless otherwise noted. symbol parameter conditions min typ max units output supplies v cc2 regulated output voltage no load l 4.75 5 5.25 v output voltage operating range (note 2) 3 5.5 v line regulation i load = 1ma, min v cc max l 25 100 mv load regulation i load = 100a to 20ma l 8 80 mv adj pin voltage i load = 100a to 20ma l 585 600 615 mv voltage ripple i load = 20ma (note 2) 1 mv rms efficiency i load = 20ma (note 2) 45 % i cc2 output short circuit current v cc2 = 0v 45 ma current limit v cc2 = C5% l 20 ma v + regulated output voltage no load l 12 12.5 13 v line regulation i load = 1ma, min v cc max l 5 30 mv load regulation i load = 100a to 20ma l 200 mv adj pin voltage i load = 100a to 20ma l 1.170 1.220 1.260 mv voltage ripple i load = 20ma (note 2) 3 mv rms efficiency i load = 20ma (note 2) 45 % i + output short circuit current v + = 0v 70 ma current limit v + = C0.5v l 20 ma v C regulated output voltage no load l C12 C12.5 C13 v line regulation i load = C1ma, min v cc max l 4 15 mv load regulation i load = 100a to 15ma i load = 100a to 15ma, h-grade l 35 35 150 mv mv adj pin voltage i load = 100a to 15ma l C1.184 C1.220 C1.256 mv voltage ripple i load = 15ma (note 2) 2 mv rms efficiency i load = 15ma (note 2) 45 % i C output short-circuit current v C = 0v 30 ma current limit v C = 0.5v, v + = 1.5ma l 10 15 ma logic/spi v ith input threshold voltage on, di1, sdoe, sck, sdi, cs 1.62v v l < 2.35v on, di1, sdoe, sck, sdi, cs 2.35v v l i1, i2, sdo2 l l l 0.25 ? v l 0.33 ? v l 0.33 ? v cc2 0.75 ? v l 0.67 ? v l 0.67 ? v cc2 v v v i inl input current l 1 a v hys input hysteresis (note 2) 150 mv v oh output high voltage do1, do2, sdo i load = C1ma, 1.62v v l < 3v i load = C4ma, 3v v l 5.5v l v l C 0.4 v o1, sck2, sdi2, cs2, i load = C4ma l v cc2 C 0.4 v v ol output low voltage do1, do2, sdo i load = 1ma, 1.62v v l < 3v i load = 4ma, 3v v l 5.5v l 0.4 v o1, sck2, sdi2, cs2, i load = 4ma l 0.4 v i sc short-circuit current 0v (do1, do2, sdo) v l 0v (o1, sck2, sdi2, cs2) v cc2 l 60 85 ma ma
ltm2883 5 2883f e lec t rical c harac t eris t ics symbol parameter conditions min typ max units i 2 c v il low level input voltage scl, sda sda2 l l 0.3 ? v l 0.3 ? v cc2 v v v ih high level input voltage scl, sda sda2 l l 0.7 ? v l 0.7 ? v cc2 v v i inl input current scl, sda = v l or 0v l 1 a v hys input hysteresis scl, sda sda2 0.05 ? v l 0.05 ? v cc2 mv mv v oh output high voltage scl2, i load = C2ma do2, i load = C2ma l l v cc2 C 0.4 v l C 0.4 v v v ol output low voltage sda, v l = 3v, i load = 3ma do2, v l = 3v, i load = 2ma scl2, i load = 2ma sda2, no load, sda = 0v, 4.5v v cc2 < 5.5v sda2, no load, sda = 0v, 3v < v cc2 < 4.5v l l l l l 0.3 0.4 0.4 0.4 0.45 0.55 v v v v v c in input pin capacitance scl, sda, sda2 (note 2) l 10 pf c b bus capacitive load scl2, standard speed (note 2) scl2, fast speed sda, sda2, sr 1v/s, standard speed (note 2) sda, sda2, sr 1v/s, fast speed l l l l 400 200 400 200 pf pf pf pf minimum bus slew rate sda, sda2 l 1 v/s i sc short-circuit current sda2 = 0, sda = v l 0v scl2 v cc2 0v do2 v l sda = 0, sda2 = v cc2 sda = v l , sda2 = 0 l 30 30 6 C1.8 100 ma ma ma ma ma esd (hbm) (note 2) isolation boundary (v cc2 , v + , v C , gnd2) to (v cc , v l , gnd) 10 kv the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. specifications apply to all options unless otherwise noted. s wi t ching c harac t eris t ics symbol parameter conditions min typ max units logic maximum data rate ix dox, c l = 15pf (note 3) l 10 mhz t phl , t plh propagation delay c l = 15pf (figure 1) l 35 60 100 ns t r rise time c l = 15pf (figure 1) ltm2883-i, do2, c l = 15pf (figure 1) l l 3 20 12.5 35 ns ns t f fall time c l = 15pf (figure 1) ltm2883-i, do2, c l = 15pf (figure 1) l l 3 20 12.5 35 ns ns spi maximum data rate bidirectional communication (note 3) unidirectional communication (note 3) l l 4 8 mhz mhz t phl , t plh propagation delay c l = 15pf (figure 1) l 35 60 100 ns t pwu output pulse width uncertainty sdi2, cs2 (note 2) C20 50 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. specifications apply to all options unless otherwise noted.
ltm2883 6 2883f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by design and not subject to production test. note 3: maximum data rate is guaranteed by other measured parameters and is not tested directly. note 4: this module includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above specified maximum operating junction temperature may result in device degradation or failure. note 5: device considered a 2-terminal device. pin group a1 through b8 shorted together and pin group k1 through l8 shorted together. symbol parameter conditions min typ max units v iso rated dielectric insulation voltage 1 minute, derived from 1 second test 2500 v rms 1 second (note 5) 4400 v common mode transient immunity ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = on = 3.3v, v cm = 1kv, t = 33ns (note 2) 30 kv/s v iorm maximum working insulation voltage (notes 2, 5) 560 400 v peak v rms partial discharge v pd = 1050v peak (notes 2, 5) 5 pc input to output resistance (notes 2, 5) 10 9 input to output capacitance (notes 2, 5) 6 pf creepage distance (note 2) 9.48 mm i sola t ion c harac t eris t ics t a = 25c. s wi t ching c harac t eris t ics symbol parameter conditions min typ max units t r rise time c l = 15pf (figure 1) l 3 12.5 ns t f fall time c l = 15pf (figure 1) l 3 12.5 ns t pzh , t pzl output enable time sdoe = , r l = 1k, c l = 15pf (figure 2) l 50 ns t phz , t plz output disable time sdoe = , r l = 1k, c l = 15pf (figure 2) l 50 ns i 2 c maximum data rate (note 3) l 400 khz t phl , t plh propagation delay scl scl2, c l = 15pf (figure 1) sda sda2, r l = open, c l = 15pf (figure 3) sda2 sda, r l = 1.1k, c l = 15pf (figure 3) l l l 150 150 200 225 250 350 ns ns ns t pwu output pulse width uncertainty sda, sda2 (note 2) C20 50 ns t hd;dat data hold time (note 2) 600 ns t r rise time sda2, c l = 200pf (figure 3) sda2, c l = 200pf (figure 3) sda, r l = 1.1k, c l = 200pf (figure 3) scl2, c l = 200pf (figure 1) l l l 40 40 40 250 300 250 250 ns ns ns ns t f fall time sda2, c l = 200pf (figure 3) sda, r l = 1.1k, c l = 200pf (figure 3) scl2, c l = 200pf (figure 1) l l l 40 40 250 250 250 ns ns ns t sp pulse width of spikes suppressed by input filter l 0 50 ns power supply power-up time on = to v cc2 (min) on = to v + (min) on = to v C (min) l l l 0.6 0.6 0.6 2 2 2.5 ms ms ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. specifications apply to all options unless otherwise noted.
ltm2883 7 2883f typical p er f or m ance c harac t eris t ics v cc2 line regulation vs load current v + line regulation vs load current v C line regulation vs load current v cc2 line regulation vs load current v + line regulation vs load current v C line regulation vs load current v cc supply current vs temperature isolated supplies vs equal load current isolated supplies vs equal load current t a = 25c, ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, gnd = gnd2 = 0v, on = v l unless otherwise noted. temperature (c) ?50 supply current (ma) 30 25 15 20 10 50 0 100 2883 g01 125 25 ?25 75 no load, refresh data only ltm2883-3 v cc = 3.3v ltm2883-5 v cc = 5v load current (ma) 0 v cc2 , v + , |v ? | voltage (v) 14 4 2 6 8 10 12 0 20 10 15 5 2883 g02 25 ltm2883-3 v cc = 3.3v v cc2 v + v ? load current (ma) 0 v cc2 , v + , |v ? | voltage (v) 14 4 2 6 8 10 12 0 20 10 15 5 2883 g03 3025 ltm2883-5 v cc = 5v v cc2 v + v ? load current (ma) 0 v cc2 voltage (v) 6.0 3.0 3.5 4.0 4.5 5.0 5.5 2.5 20 10 30 2883 g04 40 ltm2883-3 i + = i ? = 0a v cc = 3v v cc = 3.3v v cc = 3.6v load current (ma) 0 v + voltage (v) 13.0 10.0 10.5 11.0 11.5 12.0 12.5 9.0 9.5 2010 30 2883 g05 605040 v cc = 3v v cc = 3.15v v cc = 3.3v v cc = 3.6v ltm2883-3 i cc2 = i ? = 0a ?9.0 ?10.0 ?10.5 ?11.0 ?11.5 ?12.0 ?12.5 ?13.0 ?9.5 load current (ma) 0 v ? voltage (v) 20 10 2883 g06 30 v cc = 3v v cc = 3.15v v cc = 3.3v v cc = 3.6v ltm2883-3 i cc2 = i + = 0a load current (ma) 0 v cc2 voltage (v) 6.0 3.0 3.5 4.0 4.5 5.0 5.5 2.5 20 10 30 2883 g07 40 v cc = 4.5v v cc = 5v v cc = 5.5v ltm2883-5 i + = i ? = 0a load current (ma) 0 v + voltage (v) 13.0 10.0 10.5 11.0 11.5 12.0 12.5 9.0 9.5 2010 30 2883 g08 605040 v cc = 4.5v v cc = 4.75v v cc = 5v v cc = 5.5v ltm2883-5 i cc2 = i ? = 0a ?9.0 ?10.0 ?10.5 ?11.0 ?11.5 ?12.0 ?12.5 ?13.0 ?9.5 load current (ma) 0 v ? voltage (v) 20 10 30 2883 g09 40 v cc = 4.5v v cc = 4.75v v cc = 5v v cc = 5.5v ltm2883-5 i cc2 = i + = 0a
ltm2883 8 2883f typical p er f or m ance c harac t eris t ics v + load regulation vs temperature v C load regulation vs temperature v C load regulation vs temperature v cc2 efficiency v cc2 voltage and i cc current vs load current v cc2 load regulation vs temperature v cc2 load regulation vs temperature v + load regulation vs temperature t a = 25c, ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, gnd = gnd2 = 0v, on = v l unless otherwise noted. temperature (c) ?50 v cc2 voltage (v) 5.20 5.05 5.15 5.10 5.00 4.90 4.95 50 0 100 2883 g10 125 25 ?25 75 ltm2883-3 v cc = 3.3v i + = i ? = 0a i cc2 = 1ma i cc2 = 20ma temperature (c) ?50 v cc2 voltage (v) 5.20 5.05 5.15 5.10 5.00 4.90 4.95 50 0 100 2883 g11 125 25 ?25 75 ltm2883-5 v cc = 5v i + = i ? = 0a i cc2 = 1ma i cc2 = 20ma temperature (c) ?50 v + voltage (v) 12.8 12.5 12.7 12.6 12.4 12.2 12.3 50 0 100 2883 g12 125 25 ?25 75 ltm2883-3 v cc = 3.3v i cc2 = i ? = 0a i + = 1ma i + = 5ma i + = 10ma i + = 15ma i + = 20ma temperature (c) ?50 v + voltage (v) 12.7 12.5 12.6 12.4 12.1 12.2 12.3 50 0 100 2883 g13 125 25 ?25 75 i + = 1ma i + = 5ma i + = 10ma i + = 15ma i + = 20ma ltm2883-5 v cc = 5v i cc2 = i ? = 0a temperature (c) ?50 v ? voltage (v) ?12.2 ?12.5 ?12.3 ?12.4 ?12.6 ?12.8 ?12.7 50 0 100 2883 g14 125 25 ?25 75 i ? = 1ma i ? = 15ma ltm2883-3 v cc = 3.3v i cc2 = i + = 0a temperature (c) ?50 v ? voltage (v) ?12.2 ?12.5 ?12.3 ?12.4 ?12.6 50 0 100 2883 g15 125 25 ?25 75 i ? = 1ma i ? = 20ma ltm2883-5 v cc = 5v i cc2 = i + = 0a load current (ma) 0 efficiency (%) power loss (w) 60 10 20 30 40 50 0 0.6 0.4 0.2 0.3 0.1 0.5 0 20 10 30 2883 g16 40 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v efficiency power loss i + = i ? = 0a load current (ma) 0 v cc2 voltage (v) i cc current (ma) 6 1 2 3 4 5 0 150 100 50 75 25 125 0 20 10 30 2883 g17 40 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v voltage i cc current i + = i ? = 0a
ltm2883 9 2883f typical p er f or m ance c harac t eris t ics v C efficiency v C voltage and i cc current vs load current v cc2 transient response 20ma load step v + transient response 20ma load step v C transient response 20ma load step v + efficiency v + voltage and i cc current vs load current t a = 25c, ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, gnd = gnd2 = 0v, on = v l unless otherwise noted. load current (ma) 0 efficiency (%) power loss (w) 60 10 20 30 40 50 0 1.2 0.8 0.4 0.6 0.2 1.0 0 2010 30 2883 g18 5040 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v efficiency power loss i cc2 = i ? = 0a 0 2010 30 5040 load current (ma) v + voltage (v) i cc current (ma) 14 12 6 8 10 2 4 0 350 250 150 50 200 100 300 0 2883 g19 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v i cc2 = i ? = 0a voltage i cc current load current (ma) 0 efficiency (%) power loss (w) 60 10 20 30 40 50 0 0.6 0.4 0.2 0.3 0.1 0.5 0 20 10 2883 g20 30 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v efficiency power loss load current (ma) 0 v ? voltage (v) i cc current (ma) ?9.0 ?12.5 ?12.0 ?11.5 ?11.0 ?10.0 ?9.5 ?10.5 ?13.0 320 200 120 80 160 40 240 280 0 20 10 2883 g21 30 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v voltage i cc current 100s/div v cc2 100mv/div i cc2 10ma/div 2883 g22 100s/div v + 200mv/div i + 10ma/div 2883 g23 100s/div v ? 200mv/div i ? 10ma/div 2883 g24 i + = 1.5ma
ltm2883 10 2883f typical p er f or m ance c harac t eris t ics v cc supply current vs single channel data rate logic input threshold vs v l supply voltage logic output voltage vs load current v cc2 ripple v + ripple v C ripple t a = 25c, ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, gnd = gnd2 = 0v, on = v l unless otherwise noted. v cc2 noise v + noise v C noise 1ms/div 2mv/div 2883 g30 500ns/div 2mv/div 2883 g25 500ns/div 5mv/div i + = 1ma i + = 20ma 2883 g26 500ns/div 5mv/div i ? = 1ma i ? = 20ma 2883 g27 1ms/div 2mv/div 2883 g28 1ms/div 2mv/div 2883 g29 data rate (hz) 1k v cc current (ma) 70 60 20 30 40 50 10 100k 10k 1m 2883 g31 100m 10m v cc = 5v i cc2 = i + = i ? = 0 c l = 1nf c l = 330pf c l = 100pf c l = 20pf v l supply voltage (v) 1 threshold voltage (v) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 0 4 5 2 2883 g32 6 3 input rising input falling load current (ma) 0 output voltage (v) 6.0 1.0 2.0 3.0 4.0 5.0 0 21 3 2883 g33 10987654 v l = 5.5v v l = 3.3v v l = 1.62v
ltm2883 11 2883f typical p er f or m ance c harac t eris t ics v cc2 cross regulation vs v + , v C load isolated supply efficiency with equal load current power on sequence v cc2 cross regulation vs v + , v C load t a = 25c, ltm2883-3 v cc = 3.3v, ltm2883-5 v cc = 5v, v l = 3.3v, gnd = gnd2 = 0v, on = v l unless otherwise noted. 200s/div 5v/div v ? on v + v cc2 2883 g34 load current (ma) 0 v cc2 voltage (v) v + , |v ? | voltage (v) 5.2 4.9 5.0 5.1 4.8 14 7 8 9 10 12 11 13 6 20 10 30 2883 g35 40 ltm2883-3 v cc = 3.3v i cc2 = 15ma v cc2 v + v ? 0 20 10 30 40 load current (ma) v cc2 voltage (v) v + , |v ? | voltage (v) 5.2 4.9 5.0 5.1 4.8 14 7 8 9 10 12 11 13 6 2883 g36 ltm2883-5 v cc = 5v i cc2 = 15ma v cc2 v + v ? v + cross regulation vs v C load v + cross regulation vs v C load load current (ma) 0 efficiency (%) power loss (w) 60 10 20 30 40 50 0 1.0 0.8 0.4 0.6 0.2 0.7 0.3 0.5 0.1 0.9 0 20 10 2883 g37 25 15 5 ltm2883-3, v cc = 3.3v ltm2883-5, v cc = 5v efficiency power loss load current (ma) 0 v + , |v ? | voltage (v) 14 7 8 9 10 12 11 13 6 20 105 15 2883 g38 25 ltm2883-3 v cc = 3.3v v + , i + = 10ma v ? , i + = 10ma v + , i + = 15ma v ? , i + = 15ma load current (ma) 0 v + , |v ? | voltage (v) 14 7 8 9 10 12 11 13 6 20 105 25 15 30 2883 g39 35 ltm2883-5 v cc = 5v v + , i + = 10ma v ? , i + = 10ma v + , i + = 15ma v ? , i + = 15ma
ltm2883 12 2883f p in func t ions logic side do2 (a1): digital output, referenced to v l and gnd. logic output connected to i2 through isolation barrier. under the condition of an isolation communication failure this output is in a high impedance state. dnc (a2): do not connect pin. pin connected internally. scl (a3): serial i 2 c clock input, referenced to v l and gnd. logic input connected to isolated side scl2 pin through isolation barrier. clock is unidirectional from logic to isolated side. do not float. sda (a4): serial i 2 c data pin, referenced to v l and gnd. bidirectional logic pin connected to isolated side sda2 pin through isolation barrier. under the condition of an isola - tion communication failure this pin is in a high impedance state. do not float. di1 (a5): digital input, referenced to v l and gnd. logic input connected to o1 through isolation barrier. the logic state on di1 translates to the same logic state on o1. do not float. gnd (a6, b2 to b6): circuit ground. on (a7): enable. enables power and data communica- tion through the isolation barrier. if on is high the part is enabled and power and communications are functional to the isolated side. if on is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. do not float. v l (a8): logic supply. interface supply voltage for pins di1, scl, sda, do1, do2, and on. operating voltage is 3v to 5.5v. internally bypassed with 2.2f. do1 (b1): digital output, referenced to v l and gnd. logic output connected to i1 through isolation barrier. under the condition of an isolation communication failure this output is in a high impedance state. v cc (b7 to b8): supply voltage. operating voltage is 3v to 3.6v for ltm2883-3 and 4.5v to 5.5v for ltm2883-5. internally bypassed with 2.2f. isolated side i2 (l1): digital input, referenced to v cc2 and gnd2. logic input connected to do2 through isolation barrier. the logic state on i2 translates to the same logic state on do2. do not float. dnc (l2): do not connect pin. pin connected internally. scl2 (l3): serial i 2 c clock output, referenced to v cc2 and gnd2. logic output connected to logic side scl pin through isolation barrier. clock is unidirectional from logic to isolated side. scl2 has a push-pull output stage, do not connect an external pull-up device. under the condition of an isolation communication failure this output defaults to a high state. sda2 (l4): serial i 2 c data pin, referenced to v cc2 and gnd2. bidirectional logic pin connected to logic side sda pin through isolation barrier. output is biased high by a 1.8ma current source. do not connect an external pull- up device to sda2. under the condition of an isolation communication failure this output defaults to a high state. o1 (l5): digital output, referenced to v cc2 and gnd2. logic output connected to di1 through isolation barrier. under the condition of an isolation communication failure o1 defaults to a high state. v cc2 (l6): 5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to 5v. internally bypassed with 2.2f. v C (l7): C12.5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to C12.5v. internally bypassed with 1f. v + (l8): 12.5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to 12.5v. internally bypassed with 1f. i1 (k1): digital input, referenced to v cc2 and gnd2. logic input connected to do1 through isolation barrier. the logic state on i1 translates to the same logic state on do1. do not float. gnd2 (k2 to k5): isolated ground. av cc2 (k6): 5v nominal isolated supply voltage adjust. the adjust pin voltage is 600mv referenced to gnd2. av C (k7): C12.5v nominal isolated supply voltage adjust. the adjust pin voltage is C1.22v referenced to gnd2. av + (k8): 12.5v nominal isolated supply voltage adjust. the adjust pin voltage is 1.22v referenced to gnd2. (ltm2883-i)
ltm2883 13 2883f p in func t ions logic side sdo (a1): serial spi digital output, referenced to v l and gnd. logic output connected to isolated side sdo2 pin through isolation barrier. under the condition of an isolation communication failure this output is in a high impedance state. do2 (a2): digital output, referenced to v l and gnd. logic output connected to i2 through isolation barrier. under the condition of an isolation communication failure this output is in a high impedance state. sck (a3): serial spi clock input, referenced to v l and gnd. logic input connected to isolated side sck2 pin through isolation barrier. do not float. sdi (a4): serial spi data input, referenced to v l and gnd. logic input connected to isolated side sdi2 pin through isolation barrier. do not float. cs (a5): serial spi chip select, referenced to v l and gnd. logic input connected to isolated side cs2 pin through isolation barrier. do not float. sdoe (a6): serial spi data output enable, referenced to v l and gnd. a logic high on sdoe places the logic side sdo pin in a high impedance state, a logic low enables the output. do not float. on (a7): enable. enables power and data communica- tion through the isolation barrier. if on is high the part is enabled and power and communications are functional to the isolated side. if on is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. do not float. v l (a8): logic supply. interface supply voltage for pins sdi, sck, sdo, do1, do2, cs, and on. operating voltage is 1.62v to 5.5v. internally bypassed with 2.2f. do1 (b1): digital output, referenced to v l and gnd. logic output connected to i1 through isolation barrier. under the condition of an isolation communication failure this output is in a high impedance state. gnd (b2 to b6): circuit ground. v cc (b7 to b8): supply voltage. operating voltage is 3v to 3.6v for ltm2883-3 and 4.5v to 5.5v for ltm2883-5. internally bypassed with 2.2f. isolated side sdo2 (l1): serial spi digital input, referenced to v cc2 and gnd2. logic input connected to logic side sdo pin through isolation barrier. do not float. i2 (l2): digital input, referenced to v cc2 and gnd2. logic input connected to do2 through isolation barrier. the logic state on i2 translates to the same logic state on do2. do not float. sck2 (l3): serial spi clock output, referenced to v cc2 and gnd2. logic output connected to logic side sck pin through isolation barrier. under the condition of an isolation communication failure this output defaults to a low state. sdi2 (l4): serial spi data output, referenced to v cc2 and gnd2. logic output connected to logic side sdi pin through isolation barrier. under the condition of an isolation communication failure this output defaults to a low state. cs2 (l5): serial spi chip select, referenced to v cc2 and gnd2. logic output connected to logic side cs pin through isolation barrier. under the condition of an isolation com - munication failure this output defaults to a high state. v cc2 (l6): 5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to 5v. internally bypassed with 2.2f. v C (l7): C12.5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to C12.5v. internally bypassed with 1f. v + (l8): 12.5v nominal isolated supply voltage. internally generated from v cc by an isolated dc/dc converter and regulated to 12.5v. internally bypassed with 1f. i1 (k1): digital input, referenced to v cc2 and gnd2. logic input connected to do1 through isolation barrier. the logic state on i1 translates to the same logic state on do1. do not float. gnd2 (k2 to k5): isolated ground. av cc2 (k6): 5v nominal isolated supply voltage adjust. the adjust pin voltage is 600mv referenced to gnd2. av C (k7): C12.5v nominal isolated supply voltage adjust. the adjust pin voltage is C1.22v referenced to gnd2. av + (k8): 12.5v nominal isolated supply voltage adjust. the adjust pin voltage is 1.22v referenced to gnd2. (ltm2883-s)
ltm2883 14 2883f b lock diagra m 2883 bdb 2.2f 2.2f v cc v cc2 av cc2 gnd2 v l 110k 2.2f gnd on cs sdoe sdi sdo do1 do2 sck cs2 sdi2 sdo2 i1 i2 sck2 dc/dc converter isolated communi- cations interface isolated communi- cations interface reg 15k 1f v + av + 150k reg reg 16.2k 16.2k 1f av ? v ? 150k reg ltm2883-i ltm2883-s 2882 bda 2.2f 2.2f v cc v cc2 av cc2 gnd2 v l 110k 2.2f gnd on di1 do2 do1 scl sda o1 sda2 i2 i1 scl2 dc/dc converter isolated communi- cations interface isolated communi- cations interface reg 15k 1f v + av + 150k reg reg 16.2k 16.2k 1f av ? v ? 150k reg
ltm2883 15 2883f tes t c ircui t s input output c l t plh t phl t r t f 90% 10% 10% 90% ?v cc2 ?v l v l v ol v oh 0v input output input output c l 2883 f01 t plh t phl t r t f 90% 10% 10% 90% ?v l ?v cc2 v cc2 v ol v oh 0v input output figure 1. logic timing measurements figure 2. logic enable/disable time 2883 f02 sdoe t pzh t pzl t phz t plz v ol + 0.5v v oh ? 0.5v ?v l v l v oh v ol 0v 0v v l sdo sdo sdoe ?v l ?v l sdo v l or 0v 0v or v cc2 sdo2 c l r l figure 3. i 2 c timing measurements t phl t plh t f t r 30% ?v l 70% 70% 30% v ol v oh sda sda2 c l v l v ol v oh 0v sda sda2 v l r l 2883 f03 ?v cc2 t phl t plh t f t r 30% ?v cc2 70% 70% 30% ?v l v cc2 0v sda2 sda sda c l v l r l sda2
ltm2883 16 2883f a pplica t ions i n f or m a t ion overview the ltm2883 digital module isolator provides a gal - vanically-isolated robust logic interface, powered by an integrated, regulated dc/dc converter, complete with decoupling capacitors. the ltm2883 is ideal for use in networks where grounds can take on different voltages. isolation in the ltm2883 blocks high voltage differences, eliminates ground loops and is extremely tolerant of com- mon mode transients between ground planes. error-free operation is maintained through common mode events greater than 30kv/s providing excellent noise isolation. isolator module technology the ltm2883 utilizes isolator module technology to translate signals and power across an isolation barrier. signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using coreless transformers formed in the module substrate. this system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode immunity, provides a robust solution for bidirectional signal isolation. the module technology provides the means to combine the isolated signaling with multiple regulators and a powerful isolated dc/dc converter in one small package. dc/dc converter the ltm2883 contains a fully integrated dc/dc converter, including the transformer, so that no external components are necessary. the logic side contains a full-bridge driver, running at 2mhz, and is ac-coupled to a single trans- former primary. a series dc blocking capacitor prevents transformer saturation due to driver duty cycle imbalance. the transformer scales the primary voltage, and is recti - fied by a full-wave voltage doubler. this topology allows for a single diode drop, as in a center tapped full-wave bridge, and eliminates transformer saturation caused by secondary imbalances. the dc/dc converter is connected to a low dropout regula- tor (ldo) to provide a regulated 5v output. an integrated boost converter generates a regulated 14v supply and a charge pumped C14v supply. these rails are regulated to 12.5v respectively by low dropout regulators. performance of the C12.5v supply is enhanced by loading the 12.5v supply. a load current of 1.5ma is sufficient to improve static and dynamic load regulation characteristics of the C12.5v output. the increased load allows the boost regulator to operate continuously and in turn improves the regulation of the inverting charge pump. the internal power solution is sufficient to provide a mini- mum of 20ma of current from v cc2 and v + , and 15ma from v C . v cc and v cc2 are each bypassed with 2.2f ceramic capacitors, and v + and v C are bypassed with 1f ceramic capacitors. v l logic supply a separate logic supply pin v l allows the ltm2883 to in - terface with any logic signal from 1.62v to 5.5v as shown in figure 4. simply connect the desired logic supply to v l . there is no interdependency between v cc and v l ; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. v l is bypassed internally by a 2.2f capacitor. hot-plugging safely caution must be exercised in applications where power is plugged into the ltm2883s power supplies, v cc or v l , due to the integrated ceramic decoupling capacitors. the 2883 f04 on cs cs2 ltm2883-s any voltage from 1.62v to 5.5v 3v to 3.6v ltm2883-3 4.5v to 5.5v ltm2883-5 external device v l v cc gnd gnd2 sdi sdi2 sck sck2 av + v ? av ? av cc2 v + v cc2 sdo do2 sdo2 i2 do1 i1 isolation barrier sdoe figure 4. v cc and v l are independent
ltm2883 17 2883f a pplica t ions i n f or m a t ion figure 5. adjustable voltage rails parasitic cable inductance along with the high q char - acteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the ltm2883. refer to linear technology ap - plication note 88, entitled ceramic input capacitors can cause overvoltage transients for a detailed discussion and mitigation of this phenomenon. isolated supply adjustable operation the three isolated power rails may be adjusted by con- nection of a single resistor from the adjust pin of each output to its associated output voltage or to gnd2. the pre-configured voltages represent the maximums for guaranteed performance. figure 5 illustrates configura - tion of the output power rails for v cc2 = 3.3v, v + = 10v, and v C = C10v. table 1. voltage adjustment formula output voltage resistor (ax to vx) to reduce output resistor (ax to gnd2) to increase output v cc2 110k ? v cc2 ? 0.6 ( ) 5 ? v cc2 66k v cc2 ? 5 v + , v C 150k ? v + ,v ? ? 1.22 ( ) 12.5 ? v + ,v ? 183k v + ,v ? ? 12.5 channel timing uncertainty multiple channels are supported across the isolation bound- ary by encoding and decoding of the inputs and outputs. up to three signals in each direction are assembled as a serial packet and transferred across the isolation barrier. the time required to transfer all 3 bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. encoding transmission is independent for each data direction. the technique used assigns sck or scl on the logic side, and sdo2 or i2 on the isolated side, the highest priority such that there is no jitter on the associ- ated output channels, only delay. this preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. the resulting pulse width uncertainty on these low priority channels is typically 6ns, but may vary up to 44ns if the low priority channels are not encoded within the same high priority serial packet. serial peripheral interface (spi) bus the ltm2883-s provides a spi compatible isolated inter - face. the maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. chan - nel timing is detailed in figures 5 through 8 and tables 3 and 4. the spi protocol supports four unique timing configurations defined by the clock polarity (cpol) and clock phase (cpha) summarized in table 2. table 2. spi mode cpol cpha data to (clock) relationship 0 0 sample (rising) set-up (falling) 0 1 set-up (rising) sample (falling) 1 0 sample (falling) set-up (rising) 1 1 set-up (falling) sample (rising) to decrease the output voltage a resistor must be connected from the output voltage pin to the associated adjust pin. to increase the output voltage connect a resistor to the adjust pin to gnd2. use the equations listed in table 1 to calculate the resistances required to adjust each output. the output voltage adjustment range for v cc2 is 3v to 5.5v. adjustment range for v + and v C is 1.22v to approximately 13.5v. operation at low output voltages for v + or v C may result in thermal shutdown due to low dropout regulator power dissipation. 2883 f05 cs cs2 ltm2883-5s v l v cc 5v gnd gnd2 sdi sdi2 do2 sck sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 i2 do1 i1 isolation barrier 3.3v 174k 10v ?10v 530k 530k on sdoe
ltm2883 18 2883f the maximum data rate for bidirectional communication is 4mhz, based on a synchronous system, as detailed in the timing waveforms. slightly higher data rates may be achieved by skewing the clock duty cycle and minimiz- ing the sdo to sck set-up time, however the clock rate is still dominated by the system propagation delays. a discussion of the critical timing paths relative to figure?6 and 7 follows. a pplica t ions i n f or m a t ion ? cs to sck (master sample sdo, 1st sdo valid) t 0 t 1 50ns, cs to cs2 propagation delay t 1 t 1+ isolated slave device propagation (response time), asserts sdo2 t 1 t 3 50ns, sdo2 to sdo propagation delay t 3 t 5 set-up time for master sdo to sck figure 6. spi timing, bidirectional, cpha = 0 figure 7. spi timing, bidirectional, cpha = 1 2883 f06 sdo2 sdo sck2 (cpol = 1) sck (cpol = 1) sck2 (cpol = 0) sck (cpol = 0) sdi2 sdi cs2 cs = sdoe cpha = 0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 17 t 18 invalid 2883 f07 sdo2 sdo sck2 (cpol = 1) sck (cpol = 1) sck2 (cpol = 0) sck (cpol = 0) sdi2 sdi cs2 cs = sdoe cpha = 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 invalid
ltm2883 19 2883f a pplica t ions i n f or m a t ion ? sdi to sck (master data write to slave) t 2 t 4 50ns, sdi to sdi2 propagation delay t 5 t 6 50ns, sck to sck2 propagation delay t 2 t 5 50ns, sdi to sck, separate packet non-zero set-up time t 4 t 6 50ns, sdi2 to sck2, separate packet non-zero set-up time ? sdo to sck (master sample sdo, subsequent sdo valid) t 8 set-up data transition sdi and sck t 8 t 10 50ns, sdi to sdi2 and sck to sck2 propagation delay t 10 sdo2 data transition in response to sck2 t 10 t 11 50ns, sdo2 to sdo propagation delay t 11 t 12 set-up time for master sdo to sck table 3. bidirectional spi timing event description time cpha event description t 0 0, 1 asynchronous chip select, may be synchronous to sdi but may not lag by more than 3ns. logic side slave data output enabled, initial data is not equivalent to slave device data output t 0 to t 1, t 17 to t 18 0, 1 propagation delay chip select, logic to isolated side, 50ns typical t 1 0, 1 slave device chip select output data enable t 2 0 start of data transmission, data set-up 1 start of transmission, data and clock set-up. data transition must be within C13ns to 3ns of clock edge t 1 to t 3 0, 1 propagation delay of slave data, isolated to logic side, 50ns typical t 3 0, 1 slave data output valid, logic side t 2 to t 4 0 propagation delay of data, logic side to isolated side 1 propagation delay of data and clock, logic side to isolated side t 5 0, 1 logic side data sample time, half clock period delay from data set-up transition t 5 to t 6 0, 1 propagation delay of clock, logic to isolated side t 6 0, 1 isolated side data sample time t 8 0, 1 synchronous data and clock transition, logic side t 7 to t 8 0, 1 data to clock delay, must be 13ns t 8 to t 9 0, 1 clock to data delay, must be 3ns t 8 to t 10 0, 1 propagation delay clock and data, logic to isolated side t 10, t 14 0, 1 slave device data transition t 10 to t 11, t 14 to t 15 0, 1 propagation delay slave data, isolated to logic side t 11 to t 12 0, 1 slave data output to sample clock set-up time t 13 0 last data and clock transition logic side 1 last sample clock transition logic side t 13 to t 14 0 propagation delay data and clock, logic to isolated side 1 propagation delay clock, logic to isolated side t 15 0 last slave data output transition logic side 1 last slave data output and data transition, logic side t 15 to t 16 1 propagation delay data, logic to isolated side t 17 0, 1 asynchronous chip select transition, end of transmission. disable slave data output logic side t 18 0, 1 chip select transition isolated side, slave data output disabled
ltm2883 20 2883f a pplica t ions i n f or m a t ion figure 8. spi timing, unidirectional, cpha = 0 figure 9. spi timing, unidirectional, cpha = 1 2883 f08 sck2 (cpol = 1) sck (cpol = 1) sck2 (cpol = 0) sck (cpol = 0) sdi2 sdi cs2 cs = sdoe cpha = 0 t 0 t 1 t 2 t 3 t 4 t 5 t 7 t 6 t 9 t 8 t 11 t 12 2883 f09 sck2 (cpol = 1) sck (cpol = 1) sck2 (cpol = 0) sck (cpol = 0) sdi2 sdi cs2 cs = sdoe cpha = 1 t 0 t 1 t 2 t 3 t 4 t 5 t 7 t 6 t 9 t 8 t 11 t 10 t 12 maximum data rate for single direction communication, master to slave, is 8mhz, limited by the systems encod - ing/decoding scheme or propagation delay. timing details for both variations of clock phase are shown in figures 8 and 9 and table 4. additional requirements to insure maximum data rate are: ? cs is transmitted prior to (asynchronous) or within the same (synchronous) data packet as sdi ? sdi and sck set-up data transition occur within the same data packet. referencing figure 6, sdi can pre- cede sck by up to 13ns (t 7 t 8 ) or lag sck by 3ns (t 8 t 9 ) and not violate this requirement. similarly in figure 8, sdi can precede sck by up to 13ns (t 4 t 5 ) or lag sck by 3ns (t 5 t 6 ). inter-ic communication (i 2 c) bus the ltm2883-i provides an i 2 c compatible isolated inter - face, clock (scl) is unidirectional, supporting master mode only, and data (sda) is bidirectional. the maximum data
ltm2883 21 2883f a pplica t ions i n f or m a t ion rate is 400khz which supports fast-mode i 2 c. timing is detailed in figure 10. the data rate is limited by the slave acknowledge setup time (t su;ack ), consisting of the i 2 c standard minimum setup time (t su;dat ) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 350ns maximum, and the combined isolated and logic data fall time of 500ns at maximum bus load- ing. the total setup time reduces the i 2 c data hold time (t hd;dat ) to a maximum of 125ns, guaranteeing sufficient data setup time (t su;ack ). the isolated side bidirectional serial data pin, sda2, simplified schematic is shown in figure 11. an internal 1.8ma current source provides a pull-up for sda2. do not connect any other pull-up device to sda2. this current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pf in fast mode and greater than 400pf in standard mode. additional proprietary circuitry monitors the slew rate on the sda and sda2 signals to manage directional control across the isolation barrier. slew rates on both pins must be greater than 1v/s for proper operation. the logic side bidirectional serial data pin, sda, requires a pull-up resistor or current source connected to v l . follow table 4. unidirectional spi timing event description time cpha event description t 0 0, 1 asynchronous chip select, may be synchronous to sdi but may not lag by more than 3ns t 0 to t 1 0, 1 propagation delay chip select, logic to isolated side t 2 0 start of data transmission, data set-up 1 start of transmission, data and clock set-up. data transition must be within C13ns to 3ns of clock edge t 2 to t 3 0 propagation delay of data, logic side to isolated side 1 propagation delay of data and clock, logic side to isolated side t 3 0, 1 logic side data sample time, half clock period delay from data set-up transition t 3 to t 5 0, 1 clock propagation delay, clock and data transition t 4 to t 5 0, 1 data to clock delay, must be 13ns t 5 to t 6 0, 1 clock to data delay, must be 3ns t 5 to t 7 0, 1 data and clock propagation delay t 8 0 last clock and data transition 1 last clock transition t 8 to t 9 0 clock and data propagation delay 1 clock propagation delay t 9 to t 10 1 data propagation delay t 11 0, 1 asynchronous chip select transition, end of transmission t 12 0, 1 chip select transition isolated side figure 10. i 2 c timing diagram 2883 f10 sda 1 8 9 sda2 scl scl2 start t prop t su;dat t hd;dat t su;ack slave ack stop
ltm2883 22 2883f the requirements in figures 12 and 13 for the appropri- ate pull-up resistor on sda that satisfies the desired rise time specifications and v ol maximum limits for fast and standard modes. the resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve. the isolated side clock pin, scl2, has a weak push-pull output driver; do not connect an external pull-up device. scl2 is compatible with i 2 c devices without clock stretch - ing. on lightly loaded connections, a 100pf capacitor from scl2 to gnd2 or rc low-pass filter (r = 500 c?= 100pf) can be used to increase the rise and fall times and minimize noise. some consideration must be given to signal coupling between scl2 and sda2. separate these signals on a printed circuit board or route with ground between. if these signals are wired off board, twist scl2 with v cc2 and/or gnd2 and sda2 with gnd2 and/or v cc2 , do not twist scl2 and sda2 together. if coupling between scl2 and sda2 is unavoidable, place the aforementioned rc filter at the scl2 pin to reduce noise injection onto sda2. rf, magnetic field immunity the isolator module technology used within the ltm2883 has been independently evaluated, and successfully passed the rf and magnetic field immunity testing requirements per european standard en 55024, in accordance with the following test standards: en 61000-4-3 radiated, radio-frequency, electromagnetic field immunity en 61000-4-8 power frequency magnetic field immunity en 61000-4-9 pulsed magnetic field immunity tests were per formed using an unshielded test card de- signed per the data sheet pcb layout recommendations. specific limits per test are detailed in table 5. table 5. test frequency field strength en 61000-4-3 annex d 80mhz to 1ghz 10v/m 1.4mhz to 2ghz 3v/m 2ghz to 2.7ghz 1v/m en 61000-4-8 level 4 50hz and 60hz 30a/m en 61000-4-8 level 5 60hz 100a/m* en 61000-4-9 level 5 pulse 1000a/m *non iec method c bus (pf) 10 r pull_up (k) 30 25 5 10 15 20 0 100 2883 f12 1000 v = 3v v = 3.3v v = 3.6v v = 4.5v to 5.5v c bus (pf) 10 r pull_up (k) 10 9 1 3 5 7 2 4 6 8 0 100 2883 f13 1000 v = 3v v = 3.3v v = 3.6v v = 4.5v to 5.5v figure 12. maximum standard speed pull-up resistance on sda figure 13. maximum fast speed pull-up resistance on sda figure 11. isolated sda2 pin schematic 2883 f11 sda2 1.8ma from logic side to logic side glitch filter a pplica t ions i n f or m a t ion
ltm2883 23 2883f technology a pplica t ions i n f or m a t ion pcb layout the high integration of the ltm2883 makes pcb layout very simple. however, to optimize its electrical isolation characteristics, emi, and thermal performance, some layout considerations are necessary. ? under heavily loaded conditions v cc and gnd current can exceed 300ma. sufficient copper must be used on the pcb to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. similarly, the v cc2 and gnd2 conductors must be sized to support any external load current. these heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity. ? input and output decoupling is not required, since these components are integrated within the package. an ad- ditional bulk capacitor with a value of 6.8f to 22f is recommended. the high esr of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. for emi sensitive applications, an additional low esl ceramic capacitor of 1f to 4.7f, placed as close to the power and ground terminals as possible, is recommended. alternatively, a number of smaller value parallel capacitors may be used to reduce esl and achieve the same net capacitance. ? do not place copper on the pcb between the inner col - umns of pads. this area must remain open to withstand the rated isolation voltage. ? the use of solid ground planes for gnd and gnd2 is recommended for non-emi critical applications to optimize signal fidelity, thermal performance, and to minimize rf emissions due to uncoupled pcb trace conduction. the drawback of using ground planes, where emi is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between gnd and gnd2. if ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate rf emissions. ? for large ground planes a small capacitance (330pf) from gnd to gnd2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. discrete capacitance will not be as effective due to parasitic esl. in addition, volt- age rating, leakage, and clearance must be considered for component selection. embedding the capacitance within the pcb substrate provides a near ideal capacitor and eliminates component selection issues; however, the pcb must be 4 layers. care must be exercised in applying either technique to insure the voltage rating of the barrier is not compromised. the pcb layout in figures 14a and 14b shows the low emi demo board for the ltm2883. the demo board uses a combination of emi mitigation techniques, including both embedded pcb bridge capacitance and discrete gnd to gnd2 capacitors. two safety rated type y2 capacitors are used in series, manufactured by murata, part number ga342qr7gf471kw01l. the embedded capacitor ef- fectively suppresses emissions above 400mhz, whereas the discrete capacitors are more effective below 400mhz. emi performance is shown in figure 15, measured using a gigahertz transverse electromagnetic (gtem) cell and method detailed in iec 61000-4-20, testing and measure - ment techniques C emission and immunity testing in transverse electromagnetic waveguides. figure 14a. ltm2883 low emi demo board layout
ltm2883 24 2883f top layer inner layer 2 inner layer 1 bottom layer figure 14b. ltm2883 low emi demo board layout (dc1748a) a pplica t ions i n f or m a t ion
ltm2883 25 2883f a pplica t ions i n f or m a t ion figure 15. ltm2883 low emi demo board emissions typical a pplica t ions frequency (mhz) 0 ?30 dbv/m ?20 0 10 20 600 700 800 900 60 2883 f15 ?10 100 200 300 400 500 1000 30 40 50 detector = quasipeak rbw = 120khz vbw = 300khz sweep time = 17s # of points = 501 dc1748a-a dc1748a-b cispr 22 class b limit 2883 f16 ltm2883-5i 5v a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 1f k6 l8 l6 l1 k1 k2 scl c sda v cc gnd v ref ltc2301, adc sda v dd gnd ad0 ad1 refc gnd in ? in + 12 10 11 1 2 7 9 8 6 5 gnd scl 3 4 ref ltc2631a-lm12, dac ca0 r_sel scl sda v out gnd v cc 3 1 3 2 4 8 1 2 4 6 8 7 5 0.1f 0.1f 0.1f 1f 1.7k 1.7k on di1 dnc o1 v l v cc gnd sda sda2 gnd scl dnc scl2 av + v ? av ? av cc2 v + ?12.5v 12.5v 1.25v 2.5v f.s. 4v f.s. 2.5v 5v v cc2 do2 i2 do1 i1 gnd2 ? + 4 5 7 6 10v out 0.1f 12.5v ?12.5v 0.1f + ? 8 1 9 2 10 3 1/2 ltc2055 lt1991 g = 8 5 6 7 ? + 1/2 ltc2055 + ? 1f 10f 0.1f 4 5 7 6 10v in 0.1f 12.5v ?12.5v 0.1f 8 1 9 2 10 3 lt1991 g = 0.2 figure 16. isolated i 2 c 12-bit, 10v analog input and output
ltm2883 26 2883f typical a pplica t ions figure 17. isolated spi device expansion 2883 f17 on cs i2 cs2 ltm2883-3s v l v cc gnd sdi sdi2 sdoe sck do2 sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 csa mosi sck csb miso do1 i1 gnd2 a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 l1 k1 k2 74vc1g123 rx/cx cx clr a b q 3.3v 1f 1nf c csa csb miso v cc gnd mosi sck csa csb mosi sck 10k
ltm2883 27 2883f figure 18. isolated i 2 c buffer with programmable outputs 2883 f18 on di1 dnc o1 v l v cc gnd sda sda2 gnd scl enable 5v sda sclin dnc scl2 av + v ? av ? av cc2 v + v cc2 do2 i2 do1 i1 gnd2 a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 10k l1 k1 k2 v cc ltc4302-1 gnd sdain sdaout sclin conn sclout addr gpio2 gpio1 sda sclout gpio2 gpio1 3 1 2 4 5 8 10 9 7 6 8.66k 137 10k 10k 10k ltm2883-5i typical a pplica t ions
ltm2883 28 2883f typical a pplica t ions figure 19. 16-channel isolated temperature to frequency converter 2883 f19 on cs i2 cs2 ltm2883-5s v l v cc gnd sdi sdi2 sdoe sck 5v do2 sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 do1 i1 gnd2 a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 1f k6 l8 l6 l1 k1 k2 ox c oz oy iy ix 1m 1m v cc gnd x2 dg4051a ntc thermistors, murata ntsd1wd104, 100k c v cc x0 x a x1 b x3 x4 11 16 3 10 9 15 13 ?t 14 12 1 x5 gnd enable v ee x6 x7 6 7 8 5 2 4 set ltc1799 out v + div gnd 4 5 3 1 2 3.01k set ltc1799 temperature (c) frequency (khz) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 1.23 1.46 1.87 2.58 3.77 5.67 8.64 13.09 19.53 28.47 40.65 55.87 74.45 96.08 119.83 144.73 169.36 out v + div gnd 4 5 3 1 2 3.01k ?t ?t ?t ?t ?t ?t ?t x2 dg4051a c v cc x0 x a x1 b x3 x4 11 16 3 10 9 15 13 ?t 14 12 1 x5 gnd enable v ee x6 x7 6 7 8 5 2 4 ?t ?t ?t ?t ?t ?t ?t
ltm2883 29 2883f 2883 f20 on cs i2 cs2 ltm2883-5s v l v cc gnd sdi sdi2 sdoe sck 5v do2 sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 do1 i1 ?12.5v uv 12.5v enable 5v enable 12.5v uv ?12.5v enable switched 12.5v switched ?12.5v switched 5v 5v uv gnd2 a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 l1 k1 k2 v2 ltc2902 crt comp3 comp2 comp1 v3 comp4 v1 v4 v ref 3 1 2 4 5 14 16 15 13 12 v pg rdis rst t0 gnd t1 6 7 8 11 10 9 0.1f 10k 226k 9.53k 93.1k 20k 196k 100k 100k irf7509 irf7509 irlml2402 irf7509 100k 100k typical a pplica t ions figure 20. digitally switched triple power supply with undervoltage monitor
ltm2883 30 2883f typical a pplica t ions figure 21. quad 16-bit 10v output range dac ?12.5v 2883 f21 ltm2883-3s 3.3v a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 1f k6 l8 l6 l1 k1 k2 sckc mosi v cc gnd v outc ltc2654-l16 sdo cs v outa sdi sck v outb clr v outd reflo 8 7 9 11 10 13 2 v cc refout ldac refc 4 14 1 15 6 5 3 gnd porsel 12 16 3 4 2 5 1 0.1f 0.1f on cs i2 cs2 v l v cc gnd sdi sdi2 sdoe sck do2 sck2 av + v ? av ? av cc2 v + ?12.5v 12.5v v cc2 sdo cs miso sdo2 do1 i1 gnd2 ? + 4 5 7 6 10v outa 0.1f 12.5v ?12.5v 0.1f 8 1 9 2 10 3 ltc2054 4 5 7 6 10v outb 0.1f 12.5v 0.1f + ? + ? 8 1 9 2 10 3 lt1991 g = 8 ?12.5v 4 5 7 6 10v outc 0.1f 12.5v 0.1f + ? 8 1 9 2 10 3 lt1991 g = 8 ?12.5v 4 5 7 6 10v outd 0.1f 12.5v 0.1f + ? 8 1 9 2 10 3 lt1991 g = 8 0.1f lt1991 g = 8 1.25v 5v
ltm2883 31 2883f typical a pplica t ions figure 22. C48v, 200w hot swap controller with isolated i 2 c interface 2883 f22 ltm2883-5i 5v a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 1f k6 l8 l6 l1 k1 k2 scl ix ox c sda v cc gnd 10k 10k on di1 dnc o1 v l v cc gnd sda sda2 gnd scl dnc scl2 av + v ? av ? av cc2 v + v cc2 do2 i2 do1 i1 gnd2 v ee v ee v out sdai ltc4261cgn ss uvl fltin uvh adin2 scl ov sdao alert 10 8 9 11 19 5 22 6 4 3 on tmr 20 adr0 en pgi adr1 1 26 25 24 adin pgi0 pg pwrgd2 ?48v rtn ?48v input irf1310ns pwrgd1 28 27 23 v ee 13 sense 14 gate 15 intv cc 7 v in 21 drain 16 ramp 18 2 10nf 100v 0.1f 47nf 100nf 220nf 1f 0.1f 330f 100v 1k 16.9k 11.8k 453k 1k, 4 in series 1/4w each 47nf 10 10k 402k 0.008 1% 1m + 10k
ltm2883 32 2883f figure 23. 12-cell battery stack monitor with isolated spi interface and low power shutdown typical a pplica t ions on cs i2 cs2 ltm2883-3s v l v cc gnd sdi sdi2 sck do2 sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 do1 i1 gnd2 a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 l1 k1 k2 scko ltc6803-1 v mode csi cso sdo sdi sdoi scki v + c12 42 44 43 41 40 s12 wdt gpio2 gpio1 c11 s11 39 38 37 3 1 2 4 5 6 7 8 1f c cs miso v cc gnd 3.3v mosi sck s10 v ref mm tos c10 v reg c9 s9 35 36 34 33 10 9 11 12 c8 nc v temp2 v temp1 s8 c7 32 31 30 13 14 15 c6 s2 v ? s1 s7 c1 s6 c5 28 29 27 26 17 16 18 19 s5 c3 c2 s3 c4 s4 25 24 23 20 21 22 1f 1f 100k 100k 100k 100k 3.3k 3.3k 3.3k 3.3k sdoe 2883 f23 74lvc3g07
ltm2883 33 2883f typical a pplica t ions ltm2883-3i 3.3v a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 1f k6 l8 l6 l1 k1 k2 scl c sda v cc gnd 10k 10k on di1 dnc o1 v l v cc gnd sda sda2 gnd scl dnc scl2 av + v ? av ? av cc2 v + v cc2 do2 i2 do1 i1 gnd2 ltc4151 shdn adin sda scl gnd adr0 adr1 48v sense ? sense + v in v out 1.37k 1% 0.02 100k at 25c, 1% vishay 2381 6154.104 n adin is the digital code measured by the adc at the adin pin tc ln n ct ad in () . , = +? ? ? ? ? ? ? ?? < 3950 8 965 1000 1 273 40 < < 150 c 2883 f24 figure 24. isolated i 2 c voltage, current and temperature power supply monitor
ltm2883 34 2883f typical a pplica t ions ltm2883-5i 5v shutdown enable sda sclin interrupt a2 a5 a4 a3 a8 a6 b8 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 l1 k1 k2 10k 10k 100k 174k on di1 dnc o1 v l v cc gnd sda sda2 gnd scl dnc scl2 av + v ? av ? av cc2 v + v cc2 do2 i2 do1 i1 gnd2 1/4 ltc4266 phy (network physical layer chip) reset int detect byp sdain scl ad0 ad1 ad2 ad3 sdaout auto shdn1 v dd dgnd agnd v ee sense gate out q1: fairchild irfm120a or philips pht6nq10t fb1, fb2: tdk mpz2012s601a t1: pulse h609nl or coilcraft eth1-230ld 2883 f25 1f smaj58a ?48v 0.1f 0.1f 0.22f 0.25 s1b q1 s1b cmpd3003 fb2 rj45 connector fb1 t1 ? ? ? ? ? ? 75 75 10nf 10nf 1 2 3 ? ? ? ? ? ? 75 75 10nf 10nf 4 6 7 8 5 1nf figure 25. one complete isolated powered ethernet port
ltm2883 35 2883f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 32 0211 rev c ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a pin 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 detail a ?b (32 places) f g h l j k e a b c d 2 1 4 3 5678 detail b substrate 0.27 ? 0.37 2.45 ? 2.55 // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.630 0.025 ? 32x symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 3.22 0.50 2.72 0.60 0.60 nom 3.42 0.60 2.82 0.75 0.63 15.0 11.25 1.27 12.70 8.89 max 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 32 e b e e b a2 f g bga package 32-lead (15mm 11.25mm 3.42mm) (reference ltc dwg # 05-08-1851 rev c) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltm2883 36 2883f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0912 ? printed in usa r ela t e d p ar t s typical a pplica t ion precision 4ma to 20ma sink/source with current monitor 1f 0.01f on cs i2 cs2 ltm2883-3s v l v cc gnd sdi sdi2 sdoe sck 3.3v do2 sck2 av + v ? av ? av cc2 v + v cc2 sdo sdo2 do1 i1 gnd2 a2 a5 a4 a3 a8 a6 b8 3 1 2 a7 a1 b1 b2 l2 l5 l4 l3 k8 l7 k7 k6 l8 l6 l1 k1 k2 1f c cs miso v cc gnd mosi sck 2883 ta02 0.1f outin lt6660-3 gnd in ? ltc2452, adc ref v cc cs sck in + sdo gnd 1 3 7 8 5 4 6 2 v out ltc2641, dac ref gnd cs sck v dd din clr 3 1 2 4 6 8 7 5 3 2 4 7 6 ? + ltc1050 0.1f source return 12.5v ?5v sink si1555dl_n 0.1f 100k 75k 11 6 7 10 14 2 3 15 ? + ltc1100 g = 10 1k 15 0.1% 3v 5v part number description comments ltm2881 isolated rs485/rs422 module transceiver plus power 20mbps 2500v rms isolation with power in lga/bga package ltm2882 dual isolated rs232 module transceiver plus power 20mbps 2500v rms isolation with power in lga/bga package ltc4310 hot-swappable i 2 c isolators bidirectional i 2 c communication, low voltage level shifting ltc6803 multistack battery monitor individual battery cell monitoring of high voltage battery stacks, multiple devices interconnected via spi ltc2309/ltc2305/ ltc2301 12-bit, 8-/2-/1-channel, 14ksps sar adcs with i 2 c 5v, internal reference, software compatible family ltc2631/LTC2630 single 12-/10-/8-bit i 2 c or spi v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to-rail output ltc2641/ltc2642 16-/14-/12-bit v out dacs 1lsb inl/dnl, 0.5nv ? s glitch, 1s settling, 3mm 3mm dfn ltc2452/ltc2453 ultra-tiny 16-bit differential 5.5v ? adcs, spi/i 2 c 2lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot packages ltc1859/ltc1858/ ltc1857 8-channel 16-/14-/12-bit, 100ksps, 10v softspan? sar adcs with spi 5v supply, up to 10v configurable unipolar/bipolar input range, pin compatible family in ssop-28 package ltc2487/ltc2486 16-bit 2- or 4-channel ? adcs with easy drive? inputs and i 2 c/spi interface 16-bit and 24-bit ? adc family, up to 16 input channels and integrated temperature sensor ltc4303/ltc4304 hot swappable i 2 c bus buffers 2.7v to 5.5v supply, rise time acceleration, stuck bus protection, 15kv esd ltc1100 zero-drift instrumentation amplifier fixed gain of 10 or 100 lt1991 precision, pin configurable gain difference amplifier gain range C13 to +14 ltc2054/ltc2055 micropower zero-drift op amps 3v/5v/5v supply ltc4151 high voltage i 2 c current and voltage monitor wide operating range: 7v to 80v ltc4261 negative voltage hot swap? controller with adc and i 2 c monitoring floating topology allows very high voltage operation ltc1799 wide frequency range silicon oscillator 1khz to 30mhz ltc6990 timerblox? voltage controlled oscillator 488hz to 2mhz

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